Controller registers are located in the MLBAR/MUBAR registers (PCI BAR0 and BAR1) that shall be mapped to a memory space that supports in-order access and variable access widths. For many computer architectures, specifying the memory space as uncacheable produces this behavior. The host shall not issue locked accesses. The host shall access registers in their native width or aligned 32-bit accesses. Violation of either of these host requirements results in undefined behavior.
Accesses that target any portion of two or more registers are not supported.
All reserved registers and all reserved bits within registers are read-only and return 0h when read. Software shall not rely on 0h being returned.

控制器寄存器位于MLBAR / MUBAR寄存器（PCI BAR0和BAR1）中，这些寄存器应映射到支持有序访问和可变访问宽度的存储空间。 对于许多计算机体系结构，将内存空间指定为不可缓存会产生此行为。 主机不得发布锁定的访问权限。 主机应以其本机宽度或对齐的32位访问方式访问寄存器。 违反这些主机要求中的任何一个都会导致未定义的行为。
不支持以两个或多个寄存器的任何部分为目标的访问。
所有保留寄存器和寄存器中的所有保留位均为只读，读取时返回0h。 软件不应依赖于返回0h。